Apply now

JOB DESCRIPTION

We are seeking an experienced ASIC Top-Level Floorplan Physical Design Engineer to join the ASIC team at a leading semiconductor company. In this role, you will work on cutting-edge technologies driving next-generation AI and PCIe switch products, with end-to-end ownership of top-level physical design from RTL through tapeout.

Key Responsibilities:

-Own top-level chip floorplanning, including die size estimation, partitioning, clock distribution, and delivery of top-level partitions

-Drive resolution of physical integration challenges related to chip assembly and top-level design

-Collaborate closely with package, design, and methodology teams on I/O planning, bump mapping, and cross-functional integration

-Develop and enhance floorplanning methodologies using industry-standard and internal tools

-Evaluate and integrate third-party and internal IP, providing technical assessments and recommendations to meet design requirements

REQUIRED SKILLS AND EXPERIENCE

-Bachelor’s degree with 8+ years, or Master’s degree with 6+ years, of experience in top-level floorplanning, including die sizing, partitioning, clocking, and pin assignment

-Strong experience across complex SoC components such as switch fabrics, arbiters, high-speed DDR, SerDes, HBM, D2D I/O, and chiplet-based designs

-Proven expertise in resolving chip-level DRC, LVS, and EM/IR issues, with successful tapeout experience at advanced nodes

-Hands-on experience with bump planning, RDL routing, and multi-voltage domain designs

-Deep understanding of hierarchical physical design, including power grid design, structured clocking, top-level placement, and custom routing

-Demonstrated ability to work cross-functionally with design, package, and methodology teams throughout the development cycle

-Proficiency in scripting languages such as Python, Tcl, or Perl