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Title : Physical Design Engineer

Location : Minneapolis, MN

Duration : 9 Months

Compensation : $55-$62/hr

Description:

We are seeking an experienced contract Physical Design Engineer to take full ownership of the back-end implementation of a high-speed interface test chip, driving the design from synthesized netlist through GDSII tape-out in a high-impact, time-bound engagement. This role is responsible for end-to-end physical design, including full-chip floorplanning in collaboration with analog teams (custom block placement, partitioning, I/O architecture, and power domains), power distribution network design, and complete place-and-route execution using Cadence Innovus across all modes and corners. The engineer will own timing closure using Cadence Tempus, resolve violations through optimization and ECOs, and ensure power integrity through IR drop and electromigration analysis. Additionally, the role includes leading physical verification sign-off (DRC/LVS/ERC) using Mentor Calibre, supporting DFT integration and ATPG alignment, coordinating with the foundry on PDK and tape-out requirements, and maintaining thorough design documentation and ECO history. Successful delivery of a foundry-clean GDSII tape-out is the primary objective of this engagement.

Required

  • Bachelor’s, Master’s, or PhD in Electrical Engineering or related field
  • 8–15 years of physical design experience with at least one full chip tape-out as a lead/primary PD engineer
  • Strong hands-on experience with Cadence Innovus for full-chip place-and-route
  • Strong hands-on experience with Cadence Tempus for timing analysis and closure across corners
  • Experience with Mentor Calibre for DRC, LVS, and ERC sign-off
  • Experience integrating hard macros (analog blocks, memory, I/O) in mixed-signal designs
  • Proven ability to own end-to-end implementation and drive designs to tape-out independently
  • Strong problem-solving and debugging skills across timing, routing, and physical verification issues
  • Able to ramp quickly and deliver within a fixed, tape-out-driven timeline
  • Clear communicator across cross-functional teams (design, analog, verification)

Preferred

  • Experience with mixed-signal or analog-heavy physical design
  • Familiarity with high-speed I/O or pad ring design
  • Experience with multi-voltage/power domain design (UPF/CPF)
  • Experience with power integrity tools (Voltus, RedHawk, etc.)
  • Exposure to Synopsys ICC2
  • Experience with ECO flows (functional and metal-only)
  • Prior contract or startup experience with high ownership environments